Recent advancements in power semiconductor die (chip) packaging technology utilize chip embedding concepts. Standard packaging processes such as wire or clip bonding, as well as common molding techniques, are replaced with galvanic processes. The semiconductor dies also are protected by a laminate. The results are a significantly reduced package footprint, package resistance and inductance, as well as low thermal resistance. For example, dies are typically soldered to structured lead frames. During the panel lamination process, several lead frames, together with FR4 laminate, are laminated together.
Due to aligning tolerances between the lead frames and non-linear shrinkage/expansion during the lamination process caused by aligning fixing pins that keep the lead frames in position, optical measurement of die and lead frame positions and corresponding data file corrections are required. Also, warpage of the dies, lead frames and panel is relatively high due to CTE (coefficient of thermal expansion) mismatch and thickness differences between the lead frames and dies, causing differences in micro-via height and challenges in the lamination and micro-via plating processes.
Furthermore, the die attach solder is conventionally deposited on the wafer back surface before die singulation (separation) in case of diffusion solder, or is dispensed on the die pad of the lead frames or stencil printed to the wafer back surface as well. Dicing through a thick metal layer on the backside of a wafer is challenging and reduces dicing quality, lowers throughput and reduces the life time of the dicing blade. Also, part of the solder on the die backside is squeezed out during the bonding process. This ‘squeeze out’ of the die backside solder is not uniform, not easy to control and not repeatable.